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LTC2600/LTC2610/LTC2620 Octal 16-/14-/12-Bit Rail-to-Rail DACs in 16-Lead SSOP DESCRIPTIO
The LTC(R)2600/LTC2610/LTC2620 are octal 16-, 14- and 12-bit, 2.5V-to-5.5V rail-to-rail voltage-output DACs in 16-lead narrow SSOP packages. They have built-in high performance output buffers and are guaranteed monotonic. These parts establish new board-density benchmarks for 16- and 14-bit DACs and advance performance standards for output drive, crosstalk and load regulation in singlesupply, voltage-output multiples. The parts use a simple SPI/MICROWIRETM compatible 3-wire serial interface which can be operated at clock rates up to 50MHz. Daisy-chain capability and a hardware CLR function are included. The LTC2600/LTC2610/LTC2620 incorporate a power-on reset circuit. During power-up, the voltage outputs rise less than 10mV above zero scale; and after power-up, they stay at zero scale until a valid write and update take place.
, LTC and LT are registered trademarks of Linear Technology Corporation. MICROWIRE is a trademark of National Semiconductor Corporation.
FEATURES
s
s s s s s s s s
s
Smallest Pin-Compatible Octal DACs: LTC2600: 16 Bits LTC2610: 14 Bits LTC2620: 12 Bits Guaranteed 16-Bit Monotonic Over Temperature Wide 2.5V to 5.5V Supply Range Low Power Operation: 250A per DAC at 3V Individual Channel Power-Down to 1A, Max Ultralow Crosstalk between DACs (<10V) High Rail-to-Rail Output Drive (15mA, Min) Double-Buffered Digital Inputs Pin-Compatible 10-/8-Bit Versions (LTC1660/LTC1665) Tiny 16-Lead Narrow SSOP Package
APPLICATIO S
s s s s
Mobile Communications Process Control and Industrial Automation Instrumentation Automatic Test Equipment
BLOCK DIAGRA
GND 1
16 VCC
REGISTER
REGISTER
REGISTER
REGISTER
VOUT A
2
DAC A
DAC H
15 VOUT H
REGISTER
REGISTER
REGISTER
VOUT B
3
DAC B
REGISTER
DAC G
14 VOUT G
REGISTER
REGISTER
REGISTER
REGISTER
VOUT C
4
DAC C
DAC F
13 VOUT F DNL (LSB)
REGISTER
REGISTER
REGISTER
REGISTER
VOUT D
5
DAC D
DAC E
12 VOUT E
REF
6 CONTROL LOGIC DECODE
POWER-ON RESET
11
CLR
CS/LD
7
10
SDO
SCK
8
32-BIT SHIFT REGISTER
9
SDI
2600 BD
U
W
U
Differential Nonlinearity (LTC2600)
1.0 0.8 0.6 0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0 0 16384 32768 CODE 49152 65535
2600 G21
VCC = 5V VREF = 4.096V
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1
LTC2600/LTC2610/LTC2620 ABSOLUTE
(Note 1)
AXI U
RATI GS
PACKAGE/ORDER I FOR ATIO
ORDER PART NUMBER
TOP VIEW GND VOUT A VOUT B VOUT C VOUT D REF CS/LD SCK 1 2 3 4 5 6 7 8 16 VCC 15 VOUT H 14 VOUT G 13 VOUT F 12 VOUT E 11 CLR 10 SDO 9 SDI
Any Pin to GND ........................................... - 0.3V to 6V Any Pin to VCC .............................................- 6V to 0.3V Maximum Junction Temperature ......................... 125C Operating Temperature Range LTC2600C/LTC2610C/LTC2620C .......... 0C to 70C LTC2600I/LTC2610I/LTC2620I .......... - 40C to 85C Storage Temperature Range ................ - 65C to 150C Lead Temperature (Soldering, 10 sec)................ 300C
LTC2600CGN LTC2600IGN LTC2610CGN LTC2610IGN LTC2620CGN LTC2620IGN GN PART MARKING 2600 2600I 2610 2610I 2620 2620I
GN PACKAGE 16-LEAD PLASTIC SSOP
TJMAX = 125C, JA = 150C/W
Consult LTC Marketing for parts specified with wider operating temperature ranges.
The q denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. VCC = 2.5V to 5.5V, VREF VCC, VOUT unloaded, unless otherwise noted.
SYMBOL PARAMETER Resolution Monotonicity DNL INL VCC = 5V, VREF = 4.096V (Note 2) Differential Nonlinearity VCC = 5V, VREF = 4.096V (Note 2) Integral Nonlinearity VCC = 5V, VREF = 4.096V (Note 2) Load Regulation VREF = VCC = 5V, Midscale IOUT = 0mA to 15mA Sourcing IOUT = 0mA to 15mA Sinking VREF = VCC = 2.5V, Midscale IOUT = 0mA to 7.5mA Sourcing IOUT = 0mA to 7.5mA Sinking ZSE VOS Zero-Scale Error Offset Error VOS Temperature Coefficient GE Gain Error Gain Temperature Coefficient VCC = 5V, VREF = 4.096V
q
ELECTRICAL CHARACTERISTICS
CONDITIONS
MIN
q q q q q q q q
LTC2620 TYP MAX
MIN 14 14
LTC2610 TYP MAX
MIN 16 16
LTC2600 TYP MAX
UNITS Bits Bits
DC Performance 12 12 0.5 0.75 4 3 0.1 0.1 0.2 0.2 1 1 3 0.7 0.2 6.5 0.7
1 16 0.5 0.5 1 1 9 9 12 0.3 0.3 0.8 0.8 1 1 3 0.2 6.5
1 64 2 2 4 4 9 9
0.025 0.125 0.025 0.125 0.05 0.05 1 1 3 0.2 6.5 0.25 0.25 9 9
LSB/mA LSB/mA LSB/mA LSB/mA mV mV V/C
VCC = 5V, VREF = 4.096V Code = 0 q VCC = 5V, VREF = 4.096V (Note 7)
q
0.7
%FSR ppm/C
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2
U
LSB LSB
W
U
U
WW
W
LTC2600/LTC2610/LTC2620
The q denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. VCC = 2.5V to 5.5V, VREF VCC, VOUT unloaded, unless otherwise noted.
SYMBOL PSR ROUT PARAMETER Power Supply Rejection DC Output Impedance DC Crosstalk (Note 4) CONDITIONS VCC = 10% VREF = VCC = 5V, Midscale; -15mA IOUT 15mA q VREF = VCC = 2.5V, Midscale; -7.5mA IOUT 7.5mA q Due to Full Scale Output Change (Note 5) Due to Load Current Change Due to Powering Down (per Channel) VCC = 5.5V, VREF = 5.6V Code: Zero Scale; Forcing Output to VCC Code: Full Scale; Forcing Output to GND VCC = 2.5V, VREF = 2.6V Code: Zero Scale; Forcing Output to VCC Code: Full Scale; Forcing Output to GND Reference Input Input Voltage Range Resistance Capacitance IREF VCC ICC Reference Current, Power Down Mode All DACs Powered Down Positive Supply Voltage Supply Current For Specified Performance VCC = 5V (Note 3) VCC = 3V (Note 3) All DACs Powered Down (Note 3) VCC = 5V All DACs Powered Down (Note 3) VCC = 3V VCC = 2.5V to 5.5V VCC = 2.5V to 3.6V VCC = 4.5V to 5.5V VCC = 2.5V to 5.5V Load Current = -100A Load Current = +100A VIN = GND to VCC (Note 6)
q q q q q q
ELECTRICAL CHARACTERISTICS
LTC2600/LTC2610/LTC2620 MIN TYP MAX -80 0.025 0.030 10 3.5 7.3 15 15 7.5 7.5 0 11 16 90 0.001 2.5 2.6 2.0 0.35 0.10 2.4 2.0 0.8 0.6 VCC - 0.4 0.4 1 8 1 5.5 4 3.2 1 1 34 34 18 24 60 60 50 50 VCC 20 0.15 0.15
UNITS dB V V/mA V mA mA mA mA V k pF A V mA mA A A V V V V V V A pF
ISC
Short-Circuit Output Current
Normal Mode
q
Power Supply
q q q q q
Digital I/O VIH VIL VOH VOL ILK CIN Digital Input High Voltage Digital Input Low Voltage Digital Output High Voltage Digital Output Low Voltage Digital Input Leakage Digital Input Capacitance
q q q q q q q q
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3
LTC2600/LTC2610/LTC2620
The q denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. VCC = 2.5V to 5.5V, VREF VCC, VOUT unloaded, unless otherwise noted.
SYMBOL PARAMETER AC Performance tS Settling Time (Note 8) 0.024% (1LSB at 12 Bits) 0.006% (1LSB at 14 Bits) 0.0015% (1LSB at 16 Bits) 0.024% (1LSB at 12 Bits) 0.006% (1LSB at 14 Bits) 0.0015% (1LSB at 16 Bits) 7 7 9 2.7 4.8 0.80 1000 12 180 120 100 15 7 9 10 2.7 4.8 5.2 0.80 1000 12 180 120 100 15 s s s s s s V/s pF nV * s kHz nV/Hz nV/Hz VP-P CONDITIONS MIN LTC2620 TYP MAX MIN LTC2610 TYP MAX MIN LTC2600 TYP MAX UNITS
ELECTRICAL CHARACTERISTICS
Settling Time for 1LSB Step (Note 9) Voltage Output Slew Rate Capacitive Load Driving Glitch Impulse Multiplying Bandwidth en Output Voltage Noise Density Output Voltage Noise
2.7
0.80 1000 At Midscale Transition At f = 1kHz At f = 10kHz 0.1Hz to 10Hz 12 180 120 100 15
The q denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. (See Figure 1) (Note 6)
SYMBOL t1 t2 t3 t4 t5 t6 t7 t8 PARAMETER SDI Valid to SCK Setup SDI Valid to SCK Hold SCK High Time SCK Low Time CS/LD Pulse Width LSB SCK High to CS/LD High CS/LD Low to SCK High SDO Propagation Delay from SCK Falling Edge CLOAD = 10pF VCC = 4.5V to 5.5V VCC = 2.5V to 5.5V CONDITIONS
q q q q q q q q q q q
TI I G CHARACTERISTICS
VCC = 2.5V to 5.5V 4 4 9 9 10 7 7 20 45 20 7 50 ns ns ns ns ns ns ns ns ns ns ns MHz
t9 t10
Note 1: Absolute maximum ratings are those values beyond which the life of a device may be impaired. Note 2: Linearity and monotonicity are defined from code kL to code 2N - 1, where N is the resolution and kL is given by kL = 0.016(2N/VREF), rounded to the nearest whole code. For VREF = 4.096V and N = 16, kL = 256 and linearity is defined from code 256 to code 65,535. Note 3: Digital inputs at 0V or VCC. Note 4: DC crosstalk is measured with VCC = 5V and VREF = 4.096V, with the measured DAC at midscale, unless otherwise noted.
4
UW
LTC2600/LTC2610/LTC2620 MIN TYP MAX
UNITS
CLR Pulse Width CS/LD High to SCK Positive Edge SCK Frequency 50% Duty Cycle
q
Note 5: RL = 2k to GND or VCC. Note 6: Guaranteed by design and not production tested. Note 7: Inferred from measurement at code 256 (LTC2600), code 64 (LTC2610) or code 16 (LTC2620), and at fullscale. Note 8: VCC = 5V, VREF = 4.096V. DAC is stepped 1/4 scale to 3/4 scale and 3/4 scale to 1/4 scale. Load is 2k in parallel with 200pF to GND. Note 9: VCC = 5V, VREF = 4.096V. DAC is stepped 1LSB between half scale and half scale - 1. Load is 2k in parallel with 200pF to GND.
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LTC2600/LTC2610/LTC2620 TYPICAL PERFOR A CE CHARACTERISTICS
LTC2600
Integral Nonlinearity (INL)
32 24 16 DNL (LSB) INL (LSB) 8 0 -8 -16 -24 -32 0 16384 32768 CODE 49152 65535
2600 G20
VCC = 5V VREF = 4.096V
0 -0.2 -0.4 -0.6 -0.8 -1.0 0 16384 32768 CODE 49152 65535
2600 G21
INL (LSB)
DNL vs Temperature
1.0 0.8 0.6 0.4 DNL (LSB) 0.2 0 -0.2 -0.4 -16 -0.6 -0.8 -1.0 -50 -30 -10 10 30 50 TEMPERATURE (C) 70 90 -24 -32 DNL (NEG) VCC = 5V VREF = 4.096V DNL (POS) INL (LSB) 32 24 16
0 -8 INL (NEG)
DNL (LSB)
Settling to 1LSB
VOUT 100V/DIV 9.7s CS/LD 2V/DIV
VCC = 5V, VREF = 4.096V 1/4-SCALE TO 3/4-SCALE STEP RL = 2k, CL = 200pF AVERAGE OF 2048 EVENTS
UW
2600 G23
Differential Nonlinearity (DNL)
1.0 0.8 0.6 0.4 0.2 16 8 0 -8 -16 -24 VCC = 5V VREF = 4.096V 32 24
INL vs Temperature
VCC = 5V VREF = 4.096V
INL (POS)
INL (NEG)
-32 -50
-30
-10 10 30 50 TEMPERATURE (C)
70
90
2600 G22
INL vs VREF
1.5 VCC = 5.5V 1.0 INL (POS) 0.5
DNL vs VREF
VCC = 5.5V
8
DNL (POS) 0 DNL (NEG) -0.5 -1.0 -1.5
0
1
2 3 VREF (V)
4
5
2600 G24
0
1
2 3 VREF (V)
4
5
2600 G25
Settling of Full-Scale Step
VOUT 100V/DIV
12.3s
CS/LD 2V/DIV
2s/DIV
2600 G26
5s/DIV SETTLING TO 1LSB VCC = 5V, VREF = 4.096V CODE 512 TO 65535 STEP RL = 2k, CL = 200pF AVERAGE OF 2048 EVENTS
2600 G27
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LTC2600/LTC2610/LTC2620 TYPICAL PERFOR A CE CHARACTERISTICS
LTC2610
Integral Nonlinearity (INL)
8 6 4 0.4 DNL (LSB) INL (LSB) 2 0 -2 -4 -0.6 -6 -8 0 4096 8192 CODE 12288 16383
2600 G28
VCC = 5V VREF = 4.096V
LTC2620
Integral Nonlinearity (INL)
2.0 1.5 1.0 0.4 DNL (LSB) INL (LSB) 0.5 0 -0.5 -1.0 -0.6 -1.5 -2.0 0 1024 2048 CODE 3072 4095
2600 G31
VCC = 5V VREF = 4.096V
LTC2600/LTC2610/LTC2620
Current Limiting
0.10 0.08 0.06 0.04 CODE = MIDSCALE VREF = VCC = 5V VREF = VCC = 3V 1.0 0.8 0.6 0.4 OFFSET ERROR (mV) 2 1 0 -1 -2 -3 -50
VOUT (V)
0.02 0 -0.02 -0.04 -0.06 -0.08 -0.10 10 -40 -30 -20 -10 0 IOUT (mA) 20 30 40 VREF = VCC = 3V VREF = VCC = 5V
VOUT (mV)
6
UW
Differential Nonlinearity (DNL)
1.0 0.8 0.6
VOUT 100V/DIV
Settling to 1LSB
VCC = 5V VREF = 4.096V
0.2 0 -0.2 -0.4
CS/LD 2V/DIV
8.9s 2s/DIV VCC = 5V, VREF = 4.096V 1/4-SCALE TO 3/4-SCALE STEP RL = 2k, CL = 200pF AVERAGE OF 2048 EVENTS
2600 G30
-0.8 -1.0 0 4096 8192 CODE 12288 16383
2600 G29
Differential Nonlinearity (DNL)
1.0 0.8 0.6 VCC = 5V VREF = 4.096V
Settling to 1LSB
6.8s VOUT 1mV/DIV
0.2 0 -0.2 -0.4
CS/LD 2V/DIV
2s/DIV VCC = 5V, VREF = 4.096V 1/4-SCALE TO 3/4-SCALE STEP RL = 2k, CL = 200pF AVERAGE OF 2048 EVENTS
2600 G33
-0.8 -1.0 0 1024 2048 CODE 3072 4095
2600 G32
Load Regulation
CODE = MIDSCALE 3
Offset Error vs Temperature
0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0 -35 -25 -15 -5 5 IOUT (mA) 15 25 35 VREF = VCC = 3V VREF = VCC = 5V
-30
-10 10 30 50 TEMPERATURE (C)
70
90
2600 G01
2600 G02
2600 G03
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LTC2600/LTC2610/LTC2620 TYPICAL PERFOR A CE CHARACTERISTICS
LTC2600/LTC2610/LTC2620
Zero-Scale Error vs Temperature
3 2.5 ZERO-SCALE ERROR (mV) GAIN ERROR (%FSR) 2.0 1.5 1.0 0.5 0 -50 0.4 0.3 OFFSET ERROR (mV) -30 -10 10 30 50 TEMPERATURE (C) 70 90 0.2 0.1 0 -0.1 -0.2 -0.3 -30 -10 10 30 50 TEMPERATURE (C) 70 90 -0.4 -50 -2 -3 2.5
Gain Error vs VCC
0.4 0.3 0.2
GAIN ERROR (%FSR) 450 400 350 300 ICC (nA) 250 200 150
0.1 0 -0.1 -0.2 -0.3 -0.4 2.5
3
3.5
4 VCC (V)
4.5
Midscale Glitch Impulse
VOUT 10mV/DIV 12nV-s TYP
VOUT (V)
CS/LD 5V/DIV
2600 G10
2.5s/DIV
UW
2600 G04
Gain Error vs Temperature
3 2 1 0 -1
Offset Error vs VCC
3
3.5
4 VCC (V)
4.5
5
5.5
2600 G06
2600 G05
ICC Shutdown vs VCC
Large-Signal Response
VOUT 0.5V/DIV
VREF = VCC = 5V 1/4-SCALE TO 3/4-SCALE 2.5s/DIV
2600 G09
100 50
5
5.5
2600 G07
0 2.5
3
3.5
4 VCC (V)
4.5
5
5.5
2600 G08
Power-On Reset Glitch
5.0 4.5 4.0
Headroom at Rails vs Output Current
5V SOURCING
VCC 1V/DIV 4mV PEAK 4mV PEAK VOUT 10mV/DIV 250s/DIV
2600 G11
3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 0 1 2 3 456 IOUT (mA) 7 8 9 10 3V SINKING 5V SINKING 3V SOURCING
2600 G12
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LTC2600/LTC2610/LTC2620 TYPICAL PERFOR A CE CHARACTERISTICS
LTC2600/LTC2610/LTC2620
Supply Current vs Logic Voltage
2.4 2.3 2.2 2.1 ICC (mA) 2.0 1.9 1.8 1.7 1.6 1.5 0 0.5 1 1.5 2 2.5 3 3.5 LOGIC VOLTAGE (V) 4 4.5 5
CS/LD 5V/DIV
VCC = 5V SWEEP SCK, SDI AND CS/LD 0V TO VCC
Multiplying Bandwidth
0 -3 -6 -9 -12 -15 VOUT 10V/DIV
dB
-18 -21 -24 -27 -30 -33 -36 1k VCC = 5V VREF (DC) = 2V VREF (AC) = 0.2VP-P CODE = FULL SCALE 10k 100k FREQUENCY (Hz) 1M
2600 G16
Short-Circuit Output Current vs VOUT (Sinking)
0mA
10mA/DIV
0mA
VCC = 5.5V VREF = 5.6V CODE = 0 VOUT SWEPT 0V TO VCC 1V/DIV
2600 G18
10mA/DIV
8
UW
Exiting Power-Down to Midscale
VCC = 5V VREF = 2V VOUT 0.5V/DIV DACs A TO G IN POWER-DOWN MODE
Hardware CLR
VOUT 1V/DIV
CLR 5V/DIV
2.5s/DIV
2600 G14
1s/DIV
2600 G15
2600 G13
Output Voltage Noise, 0.1Hz to 10Hz
0
1
2
3
456 SECONDS
7
8
9
10
2600 G17
Short-Circuit Output Current vs VOUT (Sourcing)
VCC = 5.5V VREF = 5.6V CODE = FULL SCALE VOUT SWEPT VCC TO 0V 1V/DIV
2600 G19
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LTC2600/LTC2610/LTC2620
PIN FUNCTIONS
GND (Pin 1): Analog Ground. VOUT A to VOUT H (Pins 2-5 and 12-15): DAC Analog Voltage Outputs. The output range is 0 - VREF. REF (Pin 6): Reference Voltage Input. 0V VREF VCC. CS/LD (Pin 7): Serial Interface Chip Select/Load Input. When CS/LD is low, SCK is enabled for shifting data on SDI into the register. When CS/LD is taken high, SCK is disabled and the specified command (see Table 1) is executed. SCK (Pin 8): Serial Interface Clock Input. CMOS and TTL compatible. SDI (Pin 9): Serial Interface Data Input. Data is applied to SDI for transfer to the device at the rising edge of SCK. The LTC2600, LTC2610 and LTC2620 accept input word lengths of either 24 or 32 bits. SDO (Pin 10): Serial Interface Data Output. The serial output of the shift register appears at the SDO pin. The data transferred to the device via the SDI pin is delayed 32 SCK rising edges before being output at the next falling edge. This pin is used for daisy-chain operation. CLR (Pin 11): Asynchronous Clear Input. A logic low at this level-triggered input clears all registers and causes the DAC voltage outputs to drop to 0V. CMOS and TTL compatible. VCC (Pin 16): Supply Voltage Input. 2.5V VCC 5.5V.
U
U
U
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LTC2600/LTC2610/LTC2620
BLOCK DIAGRA
GND 1
DAC REGISTER
INPUT REGISTER
INPUT REGISTER
DAC REGISTER
VOUT A
2
DAC REGISTER
INPUT REGISTER
VOUT B
3
DAC B
INPUT REGISTER
DAC REGISTER
INPUT REGISTER
DAC REGISTER
INPUT REGISTER
VOUT C
DAC REGISTER
4
DAC REGISTER
INPUT REGISTER
VOUT D
5
DAC D
INPUT REGISTER
DAC REGISTER
REF
6 CONTROL LOGIC DECODE
CS/LD
7
SCK
8
TI I G DIAGRA
SCK
SDI t5 CS/LD t8 SDO
2600 F01
10
W
W
16 VCC DAC A DAC H 15 VOUT H DAC G 14 VOUT G DAC C DAC F 13 VOUT F DAC E 12 VOUT E POWER-ON RESET 11 CLR 10 SDO 32-BIT SHIFT REGISTER 9 SDI
2600 BD02
UW
t1 t2 1 t3 2 t4 3 23 t6 24 t10
t7
Figure 1
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LTC2600/LTC2610/LTC2620
OPERATIO
Power-On Reset
The LTC2600/LTC2610/LTC2620 clear the outputs to zero scale when power is first applied, making system initialization consistent and repeatable. For some applications, downstream circuits are active during DAC power-up, and may be sensitive to nonzero outputs from the DAC during this time. The LTC2600/ 2610/2620 contain circuitry to reduce the power-on glitch: the analog outputs typically rise less than 10mV above zero scale during power on if the power supply is ramped to 5V in 1ms or more. In general, the glitch amplitude decreases as the power supply ramp time is increased. See Power-On Reset Glitch in the Typical Performance Characteristics section. Power Supply Sequencing The voltage at REF (Pin 6) should be kept within the range - 0.3V VREF VCC + 0.3V (see Absolute Maximum Ratings). Particular care should be taken to observe these limits during power supply turn-on and turn-off sequences, when the voltage at VCC (Pin 16) is in transition. Transfer Function The digital-to-analog transfer function is k VOUT(IDEAL) = N VREF 2 where k is the decimal equivalent of the binary DAC input code, N is the resolution and VREF is the voltage at REF (Pin 6).
Table 1.
COMMAND* C3 C2 C1 C0 0 0 0 0 0 1 0 0 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Write to Input Register n Update (Power Up) DAC Register n Write to Input Register n, Update (Power Up) All n Write to and Update (Power Up) n Power Down n No Operation
*Command and address codes not shown are reserved and should not be used.
U
Serial Interface The CS/LD input is level triggered. When this input is taken low, it acts as a chip-select signal, powering-on the SDI and SCK buffers and enabling the input shift register. Data (SDI input) is transferred at the next 24 rising SCK edges. The 4-bit command, C3-C0, is loaded first; then the 4-bit DAC address, A3-A0; and finally the 16-bit data word. The data word comprises the 16-, 14- or 12-bit input code, ordered MSB-to-LSB, followed by 0, 2 or 4 don't-care bits (LTC2600, LTC2610 and LTC2620 respectively). Data can only be transferred to the device when the CS/LD signal is low.The rising edge of CS/LD ends the data transfer and causes the device to carry out the action specified in the 24-bit input word. The complete sequence is shown in Figure 2a. The command (C3-C0) and address (A3-A0) assignments are shown in Table 1. The first four commands in the table consist of write and update operations. A write operation loads a 16-bit data word from the 32-bit shift register into the input register of the selected DAC, n. An update operation copies the data word from the input register to the DAC register. Once copied into the DAC register, the data word becomes the active 16-, 14- or 12-bit input code, and is converted to an analog voltage at the DAC output. The update operation also powers up the selected DAC if it had been in power-down mode. The data path and registers are shown in the block diagram. While the minimum input word is 24 bits, it may optionally be extended to 32 bits. To use the 32-bit word width, 8 don't-care bits are transferred to the device first, followed by the 24-bit word as just described. Figure 2b
ADDRESS (n)* A3 A2 A1 A0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 1 1 1 1 0 0 1 1 0 0 1 1 1 0 1 0 1 0 1 0 1 1 DAC A DAC B DAC C DAC D DAC E DAC F DAC G DAC H All DACs
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LTC2600/LTC2610/LTC2620
OPERATIO
INPUT WORD (LTC2600)
COMMAND C3 C2 C1 C0 A3 ADDRESS A2 A1 A0 DATA (16 BITS) D15 D14 D13 D12 D11 D10 D9 MSB D8 D7 D6 D5 D4 D3 D2 D1 D0 LSB
2600 TBL01
INPUT WORD (LTC2610)
COMMAND C3 C2 C1 C0 A3 ADDRESS A2 A1 A0 DATA (14 BITS + 2 DON'T-CARE BITS) D13 D12 D11 D10 D9 MSB D8 D7 D6 D5 D4 D3 D2 D1 D0 LSB
2600 TBL02
INPUT WORD (LTC2620)
COMMAND C3 C2 C1 C0 A3 ADDRESS A2 A1 A0 D11 D10 D9 MSB DATA (12 BITS + 4 DON'T-CARE BITS) D8 D7 D6 D5 D4 D3 D2 D1 D0 LSB
2600 TBL03
shows the 32-bit sequence. The 32-bit word is required for daisy-chain operation, and is also available to accommodate microprocessors which have a minimum word width of 16 bits (2 bytes). Daisy-Chain Operation The serial output of the shift register appears at the SDO pin. Data transferred to the device from the SDI input is delayed 32 SCK rising edges before being output at the next SCK falling edge. The SDO output can be used to facilitate control of multiple serial devices from a single 3-wire serial port (i.e., SCK, SDI and CS/LD). Such a "daisy chain" series is configured by connecting SDO of each upstream device to SDI of the next device in the chain. The shift registers of the devices are thus connected in series, effectively forming a single input shift register which extends through the entire chain. Because of this, the devices can be addressed and controlled individually by simply concatenating their input words; the first instruction addresses the last device in the chain and so forth. The SCK and CS/LD signals are common to all devices in the series. In use, CS/LD is first taken low. Then the concatenated input data is transferred to the chain, using SDI of the first device as the data input. When the data transfer is complete, CS/LD is taken high, completing the instruction
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X X
X
X
X
X
sequence for all devices simultaneously. A single device can be controlled by using the no-operation command (1111) for the other devices in the chain. Power-Down Mode For power-constrained applications, power-down mode can be used to reduce the supply current whenever less than eight outputs are needed. When in power-down, the buffer amplifiers and reference inputs are disabled, and draw essentially zero current. The DAC outputs are put into a high-impedance state, and the output pins are passively pulled to ground through individual 90k resistors. When all eight DACs are powered down, the master bias generation circuit is also disabled. Input- and DAC-register contents are not disturbed during power-down. Any channel or combination of channels can be put into power-down mode by using command 0100b in combination with the appropriate DAC address, (n). The 16-bit data word is ignored. The supply and reference currents are reduced by approximately 1/8 for each DAC powered down; the effective resistance at REF (pin 6) rises accordingly, becoming a high-impedance input (typically > 1G) when all eight DACs are powered down. Normal operation can be resumed by executing any command which includes a DAC update, as shown in Table 1.
2600fa
LTC2600/LTC2610/LTC2620
OPERATIO
The selected DAC is powered up as its voltage output is updated. There is an initial delay as the DAC powers up before it begins its usual settling behavior. If less than eight DACs are in a powered-down state prior to the update command, the power-up delay is 5s. If, on the other hand, all eight DACs are powered down, then the master bias generation circuit is also disabled and must be restarted. In this case, the power-up delay is greater: 12s for VCC = 5V, 30s for VCC = 3V. Voltage Outputs Each of the 8 rail-to-rail amplifiers contained in these parts has guaranteed load regulation when sourcing or sinking up to 15mA at 5V (7.5mA at 3V). Load regulation is a measure of the amplifier's ability to maintain the rated voltage accuracy over a wide range of load conditions. The measured change in output voltage per milliampere of forced load current change is expressed in LSB/mA. DC output impedance is equivalent to load regulation, and may be derived from it by simply calculating a change in units from LSB/mA to Ohms. The amplifiers' DC output impedance is 0.025 when driving a load well away from the rails. When drawing a load current from either rail, the output voltage headroom with respect to that rail is limited by the 25 typical channel resistance of the output devices; e.g., when sinking 1mA, the minimum output voltage = 25 * 1mA = 25mV. See the graph Headroom at Rails vs Output Current in the Typical Performance Characteristics section. The amplifiers are stable driving capacitive loads of up to 1000pF. Board Layout The excellent load regulation and DC crosstalk performance of these devices is achieved in part by keeping "signal" and "power" grounds separated internally and by reducing shared internal resistance to just 0.005. The GND pin functions both as the node to which the
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reference and output voltages are referred and as a return path for power currents in the device. Because of this, careful thought should be given to the grounding scheme and board layout in order to ensure rated performance. The PC board should have separate areas for the analog and digital sections of the circuit. This keeps digital signals away from sensitive analog signals and facilitates the use of separate digital and analog ground planes which have minimal capacitive and resistive interaction with each other. Digital and analog ground planes should be joined at only one point, establishing a system star ground as close to the device's ground pin as possible. Ideally, the analog ground plane should be located on the component side of the board, and should be allowed to run under the part to shield it from noise. Analog ground should be a continuous and uninterrupted plane, except for necessary lead pads and vias, with signal traces on another layer. The GND pin of the part should be connected to analog ground. Resistance from the GND pin to system star ground should be as low as possible. Resistance here will add directly to the effective DC output impedance of the device (typically 0.025), and will degrade DC crosstalk. Note that the LTC2600/LTC2610/LTC2620 are no more susceptible to these effects than other parts of their type; on the contrary, they allow layout-based performance improvements to shine rather than limiting attainable performance with excessive internal resistance. Rail-to-Rail Output Considerations In any rail-to-rail voltage output device, the output is limited to voltages within the supply range. Since the analog outputs of the device cannot go below ground, they may limit for the lowest codes as shown in Figure 3b. Similarly, limiting can occur near full scale when the REF pin is tied to VCC. If VREF = VCC and the DAC full-scale error (FSE) is positive, the output for the highest codes limits at VCC as shown in Figure 3c. No full-scale limiting can occur if VREF is less than VCC - FSE. Offset and linearity are defined and tested over the region of the DAC transfer function where no output limiting can occur.
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OPERATIO
COMMAND WORD
ADDRESS WORD
DATA WORD
24-BIT INPUT WORD
LTC2600/LTC2610/LTC2620
Figure 2a. LTC2600 24-Bit Load Sequence (Minimum Input Word). LTC2610 SDI Data Word: 14-Bit Input Code + 2 Don't-Care Bits; LTC2620 SDI Data Word: 12-Bit Input Code + 4 Don't-Care Bits
CS/LD 6 7 14 17 D15 D14 D13 D12 D11 A2 ADDRESS WORD C0 A3 A2 A1 A0 D15 D14 D13 D12 D11 D10 D9 A1 A0 X COMMAND WORD X X X C3 C2 C1 X C3 C2 C1 C0 A3 8 9 10 13 21 11 12 18 16 20 15 19 X 22 D10 23 D9 24 D8 25 D7 DATA WORD D8 D7 D6 D5 D4 D3 D2 D1 D0 26 D6 27 D5 28 D4 29 D3 30 D2 31 D1 32 D0
SCK
1
2
3
4
5
SDI
X
X
X
X
X
DON'T CARE
SDO
X
X
X
X
X
PREVIOUS 32-BIT INPUT WORD t1 t2 SCK 17 t3 SDI SDO D15 t8 PREVIOUS D15 PREVIOUS D14 t4 D14 18
CURRENT 32-BIT INPUT WORD
YYYY F02b
Figure 2b. LTC2600 32-Bit Load Sequence (Required for Daisy-Chain Operation). LTC2610 SDI/SDO Data Word: 14-Bit Input Code + 2 Don't-Care Bits; LTC2620 SDI/SDO Data Word: 12-Bit Input Code + 4 Don't-Care Bits
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14
2 7 17 D7
YYYY F02a
CS/LD 3 4 10 13 D11 D10 D9 D8 D6 D5 D4 D3 D2 D1 D0 14 21 23 D14 D13 D12 11 12 18 24 16 20 22 C0 A3 A2 A1 A0 D15 5 6 8 9 15 19 C1
SCK C2
1
SDI
C3
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LTC2600/LTC2610/LTC2620
OPERATIO U
VREF = VCC POSITIVE FSE VREF = VCC OUTPUT VOLTAGE OUTPUT VOLTAGE INPUT CODE (c) OUTPUT VOLTAGE 0 32, 768 INPUT CODE (a) 65, 535 INPUT CODE (b)
2600 F03
0V NEGATIVE OFFSET
Figure 3. Effects of Rail-to-Rail Operation On a DAC Transfer Curve. (a) Overall Transfer Function (b) Effect of Negative Offset for Codes Near Zero Scale (c) Effect of Positive Full-Scale Error for Codes Near Full Scale
PACKAGE DESCRIPTIO
.254 MIN
.0165 .0015
RECOMMENDED SOLDER PAD LAYOUT 1 .015 .004 x 45 (0.38 0.10) .007 - .0098 (0.178 - 0.249) .016 - .050 (0.406 - 1.270) NOTE: 1. CONTROLLING DIMENSION: INCHES INCHES 2. DIMENSIONS ARE IN (MILLIMETERS) 3. DRAWING NOT TO SCALE *DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE **DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE 0 - 8 TYP .053 - .068 (1.351 - 1.727) 23 4 56 7 8 .004 - .0098 (0.102 - 0.249)
Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
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GN Package 16-Lead Plastic SSOP (Narrow .150 Inch)
(Reference LTC DWG # 05-08-1641)
.045 .005 .189 - .196* (4.801 - 4.978) 16 15 14 13 12 11 10 9 .009 (0.229) REF .150 - .165 .229 - .244 (5.817 - 6.198) .150 - .157** (3.810 - 3.988) .0250 TYP .008 - .012 (0.203 - 0.305) .0250 (0.635) BSC
GN16 (SSOP) 0502
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LTC2600/LTC2610/LTC2620
TYPICAL APPLICATIO
Schematic for LTC2600 Demonstration Circuit DC579. The Outputs Are Measured by an Onboard LTC2428
1 TP1 4 3 2 1 VSS SDA A2 A1 A0 SCL WP VCC 5 6 7 8 C3 0.1F 1 VCC TP2 R1, R3, R4 R1 are 4.99k, 1% R3 R4 VREF C1 0.1F R2 7.5k 11 CLR C2 0.1F VCC VOUT A VOUT B SCK CS 14 12 10 8 6 4 2 + + + + + + + + + + + + + + 13 11 9 7 5 3 1 8 7 9 10 MOSI MISO 1 VIN VOUT C SCK LS/LD SDI SDO GND 1 TP16 U2 LTC2600CGN VOUT D VOUT E VOUT F VOUT G VOUT H 16 2 3 4 5 12 13 14 15 1 1 1 1 1 1 1 1 1 1 VCC
U1 24LC025
5V
J1 HD2X7
VIN 2
U4 LT1236ACS8-5 VIN GND C6 0.1F 4 VOUT 6 1 5V 4.096V 2 3 JP2 VREF VREF 9 1 C7 4.7F 6.3V TP11 VREF 10 11 12 13 14 15 6 1 5VREF C8 REGULATOR 1F 16V 2 3 JP3 VCC 5V VCC 1 1 TP12 VCC TP13 GND 17 5 CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7 ZSSET
U5 LT1461ACS8-4 2 3 C9 0.1F VIN SHDN GND 4 VOUT
RELATED PARTS
PART NUMBER LTC1458/LTC1458L LTC1654 LTC1655/LTC1655L LTC1657/LTC1657L LTC1660/LTC1665 LTC1821 DESCRIPTION Quad 12-Bit Rail-to-Rail Output DACs with Added Functionality Dual 14-Bit Rail-to-Rail VOUT DAC Single 16-Bit VOUT DAC with Serial Interface in SO-8 Parrallel 5V/3V 16-Bit VOUT DAC Octal 10/8-Bit VOUT DAC in 16-Pin Narrow SSOP Parallel 16-Bit Voltage Output DAC COMMENTS LTC1458: VCC = 4.5V to 5.5V, VOUT = 0V to 4.096V LTC1458L: VCC = 2.7V to 5.5V, VOUT = 0V to 2.5V Programmable Speed/Power, 3.5s/750A, 8s/450A VCC = 5V(3V), Low Power, Deglitched Low Power, Deglitched, Rail-to-Rail VOUT VCC = 2.7V to 5.5V, Micropower, Rail-to-Rail Output Precision 16-Bit Settling in 2s for 10V Step
16 Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 q FAX: (408) 434-0507
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6 REF TP3 DAC A TP4 DAC B TP5 DAC C TP6 DAC D TP7 DAC E TP8 DAC F TP9 DAC G TP10 DAC H C10 100pF 7 MUXOUT 4 ADCIN 3 FSSET R5 7.5k R8 22 2 8 C4 0.1F C5 0.1F JP1 ON/OFF DISABLE ADC VREF VCC VCC TP14 GND TP15 GND 3 2 1 VCC VCC CSADC CSMUX 4-/8-CHANNEL MUX + 20-BIT ADC - LTC2424/LTC2428 SCK CLK DIN SD0 FO GND GND GND GND GND GND GND 6 16 18 22 27 28 23 20 25 19 21 24 26 R7 7.5k SCK R6 7.5k CS 1 U3 LTC2428CG
2600fa LT/TP 1103 1K REV A * PRINTED IN THE USA
www.linear.com
(c) LINEAR TECHNOLOGY CORPORATION 2003

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